Some prior art FIFOs are implemented using a shift register structure. One difficulty with this approach is that the data must traverse the entire length of the shift register before it can be read. This results in a fixed latency or fall-through time. Another difficulty is such a memory must be written into and read out from at the same time.
Other FIFOs are implemented using a random-access-memory (RAM) to store the information and a counter to point to the head of the queue and another counter to point to the tail. While this type of FIFO has a shorter fall-through time, the input and output can not be read and written at the same time since the memory is shared. This problem can be avoided by using a dual-ported memory, however, these memories are more complex requiring additional address decoding, bussing structure and logic circuitry.
Similarly, LIFO memories can be implemented with either a bi-directional shift register or a RAM memory to store the information and a up/down counter to point to the head of the list.
Thus, there is a continuing need in the art for less complex asynchronous FIFO and LIFO memory designs having faster read and write times.